Compal GA-037 Motherboard Schematic Circuit Diagram
Compal GA-037 Motherboard Schematic Circuit Diagram
Organization of the Motherboard Cache
You probably know that cache holds data copies from various main memory locations. Because the cache cannot contain copies of data from all of the locations in the main memory at the same time, there must be a means to determine which addresses are now copied into the cache so that data from those addresses may be retrieved from the cache rather than the main memory if we need it. Tag RAM, which is extra cache memory that carries an index of the addresses transferred into the cache, performs this job. Each cache memory line contains an address tag that stores the main memory address of the data that is presently being transferred into that cache line. If data from a certain main memory address is required, the cache controller can quickly check the address tags to determine if the requested address is in the cache (a hit) or not (a miss). If the data is in the faster cache, it may be read; if it isn't, it must be read from the considerably slower main memory.
The way the tags are organized or mapped has an impact on how the cache functions. A cache can be set associative, completely associative, or direct-mapped.
When a request for data from a given main memory address is made in a fully associative mapped cache, the address is checked against all of the address tag entries in the cache tag RAM. The relevant position in the cache is returned if the requested main memory address is located in the tag (a hit). A miss happens when the requested address is not discovered in the address tag entries, and the data must be obtained from the main memory address rather than the cache.
