ECS H61H2-M12 REV. 1.0 Schematic Circuit Diagram

ECS H61H2-M12 REV. 1.0 Schematic Circuit Diagram

ECS H61H2-M12 REV. 1.0 Schematic Circuit Diagram

Dual Independent Bus Architecture

Intel and AMD introduced the Dual Independent Bus (DIB) architecture in their sixth-generation CPUs. DIB was established to increase the bandwidth and performance of the processor bus. The CPU can access data from either of its buses immediately and in parallel, instead of sequentially, because it has two (dual) independent data I/O buses (as in a single-bus system). The main (also known as front-side) processor bus connects the CPU to the motherboard or chipset. The L2 cache of a CPU with DIB uses the second (back-side) bus, allowing it to function at much higher rates than if it shared the main processor bus.

The DIB design is made up of two buses: the L2 cache bus and the main CPU bus, also known as the front-side bus (FSB). Processors of the P6 class, such as the Pentium Pro and Core 2, as well as Athlon 64 processors, may use both buses at the same time, removing a bottleneck. The dual bus design allows the newer processors' L2 cache to function at full speed inside the processor core on its own bus, freeing up the main CPU bus (FSB) to handle regular data flow in and out of the chip. The two buses go at various speeds. The front-side bus, also known as the main CPU bus, is linked to the motherboard's speed, whereas the back-side bus, also known as the L2 cache bus, is linked to the processor core's speed. The speed of the L2 cache increases in line with the frequency of CPUs.

DIB also allows the system bus to undertake multiple simultaneous transactions (rather than single sequential transactions), which speeds up the flow of data and improves performance. In general, DIB architecture provides up to three times the bandwidth of a single-bus architecture CPU.

ECS H61H2-M12 REV. 1.0 Schematic Circuit Diagram

Free Download ECS H61H2-M12 REV. 1.0 Schematic Circuit Diagram



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