Inventec Aegis 6050A2416401 Schematic Circuit Diagram

Inventec Aegis 6050A2416401 Schematic Circuit Diagram

Inventec Aegis 6050A2416401 Schematic Circuit Diagram

How The Computer Cache Works

Consider the following illustration to understand how the L1 cache works. In this story, a human (in this example, you) eats food in order to operate as the processor, requesting and processing data from memory. The major system memory is the kitchen where food is made (typically double data rate [DDR], DDR2, or DDR3 dual inline memory module [DIMMs]). The waiter is the cache controller, and the L1 cache is the table at which you are seated.

So, here's the backstory. Suppose you begin eating at the same restaurant every day at the same hour. You walk in, take a seat, and place an order for a hot dog. Let's suppose you eat one bite (byte?) every four seconds (233MHz = about 4ns cycling) to make this story approximately true. It also takes the kitchen 60 seconds to prepare any item that you request (60ns main memory).

So, when you come, you seat down, order a hot dog, and then wait 60 seconds for your food to arrive before you can start eating. You begin eating normally after the waiter delivers the dish. You finish the hot dog fast, so you call the waiter and place an order for a hamburger. You have to wait another 60 seconds for the hamburger to be prepared.

When it arrives, you resume your normal eating pace. You order a plate of fries after you finish your hamburger. You wait again, and when the fries arrive 60 seconds later, you eat them at full speed. Finally, you decide to complete your dinner by ordering cheesecake for dessert. You may eat cheesecake at full speed after another 60 seconds of waiting. The majority of your eating experience consists of a lot of waiting, followed by brief bursts of full-speed eating.

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