Inventec Bandit M2 HD+ 6050A2514101 Schematic Circuit Diagram
Inventec Bandit M2 HD+ 6050A2514101 Schematic Circuit Diagram
Level 2 Cache
A secondary (L2) cache is used to mitigate the substantial slowdown caused by an L1 cache miss. I'll compare the L2 cache to a cart containing additional food items placed properly in the restaurant such that the waiter may collect food from the cart in only 15 seconds, using the restaurant example (few previous posts) I used to illustrate L1 cache in the previous section (verses 60 seconds from the kitchen). The L2 cache is installed on the motherboard in a real Pentium class (Socket 7) machine, which implies it operates at motherboard speed (66MHz, or 15ns in this example). Instead of making the long journey back to the kitchen to get the food and bring it back to you 60 seconds later, if you ask for something the waiter did not bring to your table in advance, he may first check the cart where he has stored additional products. If the item requested is available, he will return it in 15 seconds. In practice, this means that instead of slowing down from 233MHz to 16MHz while waiting for data from the 60ns main memory, the system may obtain data from the 15ns (66MHz) L2 cache. As a result, the system's frequency drops from 233MHz to 66MHz.
